Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
[yosys.git] / tests / svinterfaces / svinterface_at_top_ref.v
1
2 module TopModule(
3 input logic clk,
4 input logic rst,
5 input logic [1:0] sig,
6 input logic flip,
7 output logic [15:0] passThrough,
8 output logic [21:0] outOther,
9 input logic interfaceInstanceAtTop_setting,
10 output logic [2:0] interfaceInstanceAtTop_other_setting,
11 output logic [1:0] interfaceInstanceAtTop_mysig_out,
12 output logic [15:0] interfaceInstanceAtTop_passThrough,
13 output logic [1:0] sig_out);
14
15
16 logic MyInterfaceInstance_setting;
17 logic [3:0] MyInterfaceInstance_other_setting;
18 logic [1:0] MyInterfaceInstance_mysig_out;
19
20 SubModule1 u_SubModule1 (
21 .clk(clk),
22 .rst(rst),
23 .u_MyInterface_setting(MyInterfaceInstance_setting),
24 .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
25 .u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
26 .u_MyInterfaceFromTop_setting(interfaceInstanceAtTop_setting),
27 .u_MyInterfaceFromTop_other_setting(interfaceInstanceAtTop_other_setting),
28 .u_MyInterfaceFromTop_mysig_out(interfaceInstanceAtTop_mysig_out),
29 .u_MyInterfaceFromTop_passThrough(interfaceInstanceAtTop_passThrough),
30 .outOther(outOther),
31 .passThrough (passThrough),
32 .sig (sig)
33 );
34
35 assign sig_out = MyInterfaceInstance_mysig_out;
36
37
38 assign MyInterfaceInstance_setting = flip;
39
40 endmodule
41
42
43 module SubModule1(
44 input logic clk,
45 input logic rst,
46 input logic u_MyInterface_setting,
47 output logic [3:0] u_MyInterface_other_setting,
48 output logic [1:0] u_MyInterface_mysig_out,
49 output logic [21:0] outOther,
50 input logic [1:0] sig,
51 input logic u_MyInterfaceFromTop_setting,
52 output logic [2:0] u_MyInterfaceFromTop_other_setting,
53 output logic [1:0] u_MyInterfaceFromTop_mysig_out,
54 output logic [14:0] u_MyInterfaceFromTop_passThrough,
55 output logic [15:0] passThrough
56 );
57
58 always @(posedge clk or posedge rst)
59 if(rst)
60 u_MyInterface_mysig_out <= 0;
61 else begin
62 if(u_MyInterface_setting)
63 u_MyInterface_mysig_out <= sig;
64 else
65 u_MyInterface_mysig_out <= ~sig;
66 end
67
68 logic MyInterfaceInstanceInSub_setting;
69 logic [21:0] MyInterfaceInstanceInSub_other_setting;
70 logic [1:0] MyInterfaceInstanceInSub_mysig_out;
71
72 assign u_MyInterfaceFromTop_mysig_out = u_MyInterfaceFromTop_setting ? 10 : 20;
73
74 SubModule2 u_SubModule2 (
75 .clk(clk),
76 .rst(rst),
77 .u_MyInterfaceInSub2_setting(u_MyInterface_setting),
78 .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
79 .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
80 .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
81 .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
82 .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
83 .passThrough (passThrough)
84 );
85 assign outOther = MyInterfaceInstanceInSub_other_setting;
86
87 assign MyInterfaceInstanceInSub_setting = 0;
88 assign MyInterfaceInstanceInSub_mysig_out = sig;
89
90 endmodule
91
92 module SubModule2(
93
94 input logic clk,
95 input logic rst,
96 input logic u_MyInterfaceInSub2_setting,
97 output logic [3:0] u_MyInterfaceInSub2_other_setting,
98 input logic [1:0] u_MyInterfaceInSub2_mysig_out,
99 input logic u_MyInterfaceInSub3_setting,
100 output logic [21:0] u_MyInterfaceInSub3_other_setting,
101 input logic [1:0] u_MyInterfaceInSub3_mysig_out,
102 output logic [15:0] passThrough
103
104 );
105
106 always @(u_MyInterfaceInSub3_mysig_out) begin
107 if (u_MyInterfaceInSub3_mysig_out == 2'b00)
108 u_MyInterfaceInSub3_other_setting[21:0] = 1000;
109 else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
110 u_MyInterfaceInSub3_other_setting[21:0] = 2000;
111 else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
112 u_MyInterfaceInSub3_other_setting[21:0] = 3000;
113 else
114 u_MyInterfaceInSub3_other_setting[21:0] = 4000;
115 end
116
117 assign passThrough[7:0] = 124;
118 assign passThrough[15:8] = 200;
119
120 endmodule