Support for SystemVerilog interfaces as a port in the top level module + test case
[yosys.git] / tests / svinterfaces / svinterface_at_top_tb.v
1 `timescale 1ns/10ps
2
3 module svinterface_at_top_tb;
4
5
6 logic clk;
7 logic rst;
8 logic [21:0] outOther;
9 logic [1:0] sig;
10 logic [1:0] sig_out;
11 logic flip;
12 logic [15:0] passThrough;
13 integer outfile;
14
15 logic interfaceInstanceAtTop_setting;
16 logic [2:0] interfaceInstanceAtTop_other_setting;
17 logic [1:0] interfaceInstanceAtTop_mysig_out;
18 logic [15:0] interfaceInstanceAtTop_passThrough;
19
20
21 TopModule u_dut (
22 .clk(clk),
23 .rst(rst),
24 .outOther(outOther),
25 .sig(sig),
26 .flip(flip),
27 .passThrough(passThrough),
28 .interfaceInstanceAtTop_setting(interfaceInstanceAtTop_setting),
29 .interfaceInstanceAtTop_other_setting(interfaceInstanceAtTop_other_setting),
30 .interfaceInstanceAtTop_mysig_out(interfaceInstanceAtTop_mysig_out),
31 .interfaceInstanceAtTop_passThrough(interfaceInstanceAtTop_passThrough),
32 .sig_out(sig_out)
33 );
34
35 initial begin
36 clk = 0;
37 while(1) begin
38 clk = ~clk;
39 #50;
40 end
41 end
42
43 initial begin
44 outfile = $fopen("output.txt");
45 rst = 1;
46 interfaceInstanceAtTop_setting = 0;
47 sig = 0;
48 flip = 0;
49 @(posedge clk);
50 #(2);
51 rst = 0;
52 @(posedge clk);
53 for(int j=0;j<2;j++) begin
54 for(int i=0;i<20;i++) begin
55 #(2);
56 flip = j;
57 sig = i;
58 @(posedge clk);
59 end
60 end
61 $finish;
62 end
63
64 always @(negedge clk) begin
65 $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
66 end
67
68 endmodule