Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
[yosys.git] / tests / svinterfaces / svinterface_at_top_wrapper.v
1 `timescale 1ns/10ps
2
3 module svinterface_at_top_wrapper(
4 input logic clk,
5 input logic rst,
6 output logic [21:0] outOther,
7 input logic [1:0] sig,
8 output logic [1:0] sig_out,
9 input logic flip,
10 output logic [15:0] passThrough,
11
12 input logic interfaceInstanceAtTop_setting,
13 output logic [2:0] interfaceInstanceAtTop_other_setting,
14 output logic [1:0] interfaceInstanceAtTop_mysig_out,
15 output logic [15:0] interfaceInstanceAtTop_passThrough,
16 );
17
18
19 TopModule u_dut (
20 .clk(clk),
21 .rst(rst),
22 .outOther(outOther),
23 .sig(sig),
24 .flip(flip),
25 .passThrough(passThrough),
26 .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting),
27 .\interfaceInstanceAtTop.other_setting(interfaceInstanceAtTop_other_setting),
28 .\interfaceInstanceAtTop.mysig_out(interfaceInstanceAtTop_mysig_out),
29 .\interfaceInstanceAtTop.passThrough(interfaceInstanceAtTop_passThrough),
30 .sig_out(sig_out)
31 );
32
33 endmodule