tests/svtypes/enum_simple.sv

   1
   2 module enum_simple(input clk, input rst);
   3
   4         enum {s0, s1, s2, s3} test_enum;
   5         typedef enum logic [1:0] {
   6                 ts0, ts1, ts2, ts3
   7         } states_t;
   8         states_t state;
   9         (states_t) state1;
  10         states_t enum_const = ts1;
  11
  12         always @(posedge clk) begin
  13                 if (rst) begin
  14                         test_enum <= s3;
  15                         state <= ts0;
  16                 end else begin
  17                         //test_enum
  18                         if (test_enum == s0)
  19                                 test_enum <= s1;
  20                         else if (test_enum == s1)
  21                                 test_enum <= s2;
  22                         else if (test_enum == s2)
  23                                 test_enum <= s3;
  24                         else if (test_enum == s3)
  25                                 test_enum <= s0;
  26                         else
  27                                 assert(1'b0); //should be unreachable
  28
  29                         //state
  30                         if (state == ts0)
  31                                 state <= ts1;
  32                         else if (state == ts1)
  33                                 state <= ts2;
  34                         else if (state == ts2)
  35                                 state <= ts0;
  36                         else
  37                                 assert(1'b0); //should be unreachable
  38                 end
  39         end
  40
  41         always @(*) begin
  42                 assert(state != 2'h3);
  43                 assert(s0 == '0);
  44                 assert(ts0 == '0);
  45                 assert(enum_const == ts1);
  46         end
  47
  48 endmodule