Add ability to override verilog mode for verific -f command
[yosys.git] / tests / svtypes / multirange_subarray_access.ys
1 logger -expect error "Insufficient number of array indices for a." 1
2 read_verilog -sv <<EOT
3 module foo;
4 logic a [6:0][4:0][1:0];
5 logic b [1:0];
6
7 assign a[0][0][0] = 1'b0;
8 assign a[0][0][1] = 1'b1;
9 assign b = a[0][0];
10
11 endmodule
12 EOT