Add ability to override verilog mode for verific -f command
[yosys.git] / tests / svtypes / static_cast_simple.sv
1 module top;
2 wire [7:0] a, b, c, d;
3 assign a = 8'd16;
4 assign b = 8'd16;
5 assign c = (a * b) >> 8;
6 assign d = (16'(a) * b) >> 8;
7
8 parameter P = 16;
9
10 wire signed [7:0] s0, s1, s2;
11 wire [7:0] u0, u1, u2, u3, u4, u5, u6;
12 assign s0 = -8'd1;
13 assign s1 = 4'(s0);
14 assign s2 = 4'(unsigned'(s0));
15 assign u0 = -8'd1;
16 assign u1 = 4'(u0);
17 assign u2 = 4'(signed'(u0));
18 assign u3 = 8'(4'(s0));
19 assign u4 = 8'(4'(u0));
20 assign u5 = 8'(4'(signed'(-8'd1)));
21 assign u6 = 8'(4'(unsigned'(-8'd1)));
22
23 wire [8:0] n0, n1, n2, n3, n4, n5, n6, n7, n8, n9;
24 assign n0 = s1;
25 assign n1 = s2;
26 assign n2 = 9'(s1);
27 assign n3 = 9'(s2);
28 assign n4 = 9'(unsigned'(s1));
29 assign n5 = 9'(unsigned'(s2));
30 assign n6 = 9'(u0);
31 assign n7 = 9'(u1);
32 assign n8 = 9'(signed'(u0));
33 assign n9 = 9'(signed'(u1));
34
35 always_comb begin
36 assert(c == 8'b0000_0000);
37 assert(d == 8'b0000_0001);
38
39 assert((P + 1)'(a) == 17'b0_0000_0000_0001_0000);
40 assert((P + 1)'(d - 2) == 17'b1_1111_1111_1111_1111);
41
42 assert(s0 == 8'b1111_1111);
43 assert(s1 == 8'b1111_1111);
44 assert(s2 == 8'b0000_1111);
45 assert(u0 == 8'b1111_1111);
46 assert(u1 == 8'b0000_1111);
47 assert(u2 == 8'b1111_1111);
48 assert(u3 == 8'b1111_1111);
49 assert(u4 == 8'b0000_1111);
50 assert(u5 == 8'b1111_1111);
51 assert(u6 == 8'b0000_1111);
52
53 assert(n0 == 9'b1_1111_1111);
54 assert(n1 == 9'b0_0000_1111);
55 assert(n2 == 9'b1_1111_1111);
56 assert(n3 == 9'b0_0000_1111);
57 assert(n4 == 9'b0_1111_1111);
58 assert(n5 == 9'b0_0000_1111);
59 assert(n6 == 9'b0_1111_1111);
60 assert(n7 == 9'b0_0000_1111);
61 assert(n8 == 9'b1_1111_1111);
62 assert(n9 == 9'b0_0000_1111);
63 end
64 endmodule