Add ability to override verilog mode for verific -f command
[yosys.git] / tests / svtypes / struct_simple.sv
1 module top;
2 localparam BITS=8;
3
4 struct packed {
5 logic a;
6 logic[BITS-1:0] b;
7 byte c;
8 logic x, y;
9 } s;
10
11 struct packed signed {
12 integer a;
13 logic[15:0] b;
14 logic[7:0] c;
15 bit [7:0] d;
16 } pack1;
17
18 struct packed {
19 byte a;
20 struct packed {
21 byte x, y;
22 } b;
23 } s2;
24
25 assign s.a = '1;
26 assign s.b = '1;
27 assign s.c = 8'hAA;
28 assign s.x = '1;
29 logic[7:0] t;
30 assign t = s.b;
31 assign pack1.a = 42;
32 assign pack1.b = 16'hAAAA;
33 assign pack1.c = '1;
34 assign pack1.d = 8'h55;
35 assign s2.b.x = 'h42;
36
37 always_comb assert(s.a == 1'b1);
38 always_comb assert(s.c == 8'hAA);
39 always_comb assert(s.x == 1'b1);
40 always_comb assert(t == 8'hFF);
41 always_comb assert(pack1.a == 42);
42 always_comb assert(pack1.b == 16'hAAAA);
43 always_comb assert(pack1.c == 8'hFF);
44 always_comb assert(pack1[15:8] == 8'hFF);
45 always_comb assert(pack1.d == 8'h55);
46 always_comb assert(s2.b.x == 'h42);
47
48 endmodule