Add ability to override verilog mode for verific -f command
[yosys.git] / tests / svtypes / typedef_initial_and_assign.ys
1 logger -expect-no-warnings
2 logger -expect warning "reg '\\var_12' is assigned in a continuous assignment" 1
3 logger -expect warning "reg '\\var_13' is assigned in a continuous assignment" 1
4 logger -expect warning "reg '\\var_14' is assigned in a continuous assignment" 1
5 logger -expect warning "reg '\\var_15' is assigned in a continuous assignment" 1
6 logger -expect warning "reg '\\var_16' is assigned in a continuous assignment" 1
7 logger -expect warning "reg '\\var_17' is assigned in a continuous assignment" 1
8 logger -expect warning "reg '\\var_18' is assigned in a continuous assignment" 1
9 logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1
10
11 read_verilog -sv typedef_initial_and_assign.sv
12 hierarchy; proc; opt
13 select -module top
14 sat -verify -seq 1 -tempinduct -prove-asserts -show-all