Add ability to override verilog mode for verific -f command
[yosys.git] / tests / svtypes / typedef_package.sv
1 package pkg;
2 typedef logic [7:0] uint8_t;
3 typedef enum logic [7:0] {bb=8'hBB, cc=8'hCC} enum8_t;
4
5 localparam uint8_t PCONST = cc;
6 parameter uint8_t PCONST_COPY = PCONST;
7 endpackage
8
9 module top;
10
11 (* keep *) pkg::uint8_t a = 8'hAA;
12 (* keep *) pkg::enum8_t b_enum = pkg::bb;
13
14 always_comb assert(a == 8'hAA);
15 always_comb assert(b_enum == 8'hBB);
16 always_comb assert(pkg::PCONST == pkg::cc);
17 always_comb assert(pkg::PCONST_COPY == pkg::cc);
18
19 endmodule