Merge branch 'master' of github.com:YosysHQ/yosys
[yosys.git] / tests / svtypes / typedef_scopes.sv
1
2 typedef logic [3:0] outer_uint4_t;
3
4 module top;
5
6 (outer_uint4_t) u4_i = 8'hA5;
7 always @(*) assert(u4_i == 4'h5);
8
9 typedef logic [3:0] inner_type;
10 (inner_type) inner_i1 = 8'h5A;
11 always @(*) assert(inner_i1 == 4'hA);
12
13 if (1) begin: genblock
14 typedef logic [7:0] inner_type;
15 (inner_type) inner_gb_i = 8'hA5;
16 always @(*) assert(inner_gb_i == 8'hA5);
17 end
18
19 (inner_type) inner_i2 = 8'h42;
20 always @(*) assert(inner_i2 == 4'h2);
21
22
23 endmodule