Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
[yosys.git] / tests / svtypes / typedef_simple.sv
1 module top;
2
3 typedef logic [1:0] uint2_t;
4 typedef logic signed [3:0] int4_t;
5 typedef logic signed [7:0] int8_t;
6 typedef int8_t char_t;
7
8 (* keep *) uint2_t int2 = 2'b10;
9 (* keep *) int4_t int4 = -1;
10 (* keep *) int8_t int8 = int4;
11 (* keep *) char_t ch = int8;
12
13
14 always @* assert(int2 == 2'b10);
15 always @* assert(int4 == 4'b1111);
16 always @* assert(int8 == 8'b11111111);
17 always @* assert(ch == 8'b11111111);
18
19 endmodule