Add ability to override verilog mode for verific -f command
[yosys.git] / tests / svtypes / typedef_struct.sv
1 package p;
2
3 typedef struct packed {
4 byte a;
5 byte b;
6 } p_t;
7
8 endpackage
9
10
11 module top;
12
13 typedef logic[7:0] t_t;
14
15 typedef struct packed {
16 bit a;
17 logic[7:0] b;
18 t_t t;
19 } s_t;
20
21 s_t s;
22 s_t s1;
23
24 p::p_t ps;
25
26 assign s.a = '1;
27 assign s.b = '1;
28 assign s.t = 8'h55;
29 assign s1 = s;
30 assign ps.a = 8'hAA;
31 assign ps.b = 8'h55;
32
33 always_comb begin
34 assert(s.a == 1'b1);
35 assert(s.b == 8'hFF);
36 assert(s.t == 8'h55);
37 assert(s1.t == 8'h55);
38 assert(ps.a == 8'hAA);
39 assert(ps.b == 8'h55);
40 end
41
42 endmodule