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Add typedef input/output test
[yosys.git] / tests / svtypes / typedef_struct_port.ys
1 read_verilog -sv typedef_struct_port.sv
2 hierarchy; proc; opt
3 select -module top
4 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
5 select -module test_parser
6 sat -verify -seq 1 -tempinduct -prove-asserts -show-all