tests/techmap/abc9.ys

   1 read_verilog <<EOT
   2 `define N 256
   3 module top(input [`N-1:0] a, output o);
   4 wire [`N-2:0] w;
   5 assign w[0] = a[0] & a[1];
   6 genvar i;
   7 generate for (i = 1; i < `N-1; i++)
   8 assign w[i] = w[i-1] & a[i+1];
   9 endgenerate
  10 assign o = w[`N-2];
  11 endmodule
  12 EOT
  13 simplemap
  14 dump
  15 design -save gold
  16
  17 abc9 -lut 4
  18
  19 design -load gold
  20 abc9 -lut 4 -fast
  21
  22 design -load gold
  23 scratchpad -copy abc9.script.default.area abc9.script
  24 abc9 -lut 4
  25
  26 design -load gold
  27 scratchpad -copy abc9.script.default.fast abc9.script
  28 abc9 -lut 4
  29
  30 design -load gold
  31 scratchpad -copy abc9.script.flow abc9.script
  32 abc9 -lut 4
  33
  34 design -load gold
  35 scratchpad -copy abc9.script.flow2 abc9.script
  36 abc9 -lut 4
  37
  38 design -load gold
  39 scratchpad -copy abc9.script.flow3 abc9.script
  40 abc9 -lut 4