3 module top(input [`N-1:0] a, output o);
5 assign w[0] = a[0] & a[1];
7 generate for (i = 1; i < `N-1; i++)
8 assign w[i] = w[i-1] & a[i+1];
23 scratchpad -copy abc9.script.default.area abc9.script
27 scratchpad -copy abc9.script.default.fast abc9.script
31 scratchpad -copy abc9.script.flow abc9.script
35 scratchpad -copy abc9.script.flow2 abc9.script
39 scratchpad -copy abc9.script.flow3 abc9.script
44 module top(input a, b, output o);
45 (* keep *) wire w = a & b;
51 equiv_opt -assert abc9 -lut 4
53 select -assert-count 2 t:$lut
57 read_verilog -icells <<EOT
58 module top(input a, b, output o);
60 (* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
66 equiv_opt -assert abc9 -lut 4
68 select -assert-count 1 t:$lut
69 select -assert-count 1 t:$_AND_
73 read_verilog -icells <<EOT
74 module top(input a, b, output o);
80 select -assert-count 1 t:$lut
81 select -assert-none t:$lut t:* %D