tests/techmap/autopurge.ys

   1 # https://github.com/YosysHQ/yosys/issues/1381
   2 read_verilog <<EOT
   3 module sub(input i, output o, (* techmap_autopurge *) input j);
   4 foobar f(i, o, j);
   5 endmodule
   6 EOT
   7 design -stash techmap
   8
   9 read_verilog <<EOT
  10 (* blackbox *)
  11 module sub(input i, output o, input j);
  12 endmodule
  13
  14 (* blackbox *)
  15 module foobar(input i, output o, input j);
  16 endmodule
  17
  18 module top(input i, output o);
  19 sub s0(i, o);
  20 endmodule
  21 EOT
  22
  23 techmap -map %techmap
  24 hierarchy
  25 check -assert
  26
  27 # https://github.com/YosysHQ/yosys/issues/1391
  28 design -reset
  29 read_verilog <<EOT
  30 module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
  31 foobar f(i, o, j);
  32 endmodule
  33 EOT
  34 design -stash techmap
  35
  36 read_verilog <<EOT
  37 (* blackbox *)
  38 module sub(input i, output o, input j);
  39 endmodule
  40
  41 (* blackbox *)
  42 module foobar(input i, output o, input j);
  43 endmodule
  44
  45 module top(input i, output o);
  46 sub s0(i, o);
  47 endmodule
  48 EOT
  49
  50 techmap -map %techmap
  51 hierarchy
  52 check -assert
  53
  54 read_verilog -overwrite <<EOT
  55 module top(input i, output o);
  56 wire j;
  57 sub s0(i, o, j);
  58 endmodule
  59 EOT
  60
  61 techmap -map %techmap
  62 hierarchy