tests/techmap/bug2332.ys

   1 read_verilog <<EOT
   2 module top(input [31:0] a, input signed [2:0] x, output [2:0] o);
   3
   4 wire [5:0] t = x * 3;
   5 assign o = a >> t;
   6
   7 endmodule
   8 EOT
   9
  10 wreduce
  11 equiv_opt -assert peepopt