tests/techmap/bug2972.ys

   1 read_verilog -specify <<EOT
   2 (* abc9_box, blackbox*)
   3 module box(input clk, d, output reg q, output do);
   4 parameter P = 0;
   5 always @(posedge clk)
   6     q <= d;
   7 assign do = d;
   8 specify
   9     (posedge clk => (q : d)) = 1;
  10     (d => do) = 1;
  11 endspecify
  12 endmodule
  13
  14 module top(input clk, d, output q);
  15 box i1(clk, d, q);
  16 endmodule
  17 EOT
  18 hierarchy
  19 abc9 -lut 4
  20 abc9 -lut 4