tests/techmap/cmp2lcu.ys

   1 read_verilog <<EOT
   2 module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
   3 assign gtu = a > b;
   4 assign gts = $signed(a) > $signed(b);
   5 assign ltu = a < b;
   6 assign lts = $signed(a) < $signed(b);
   7 assign geu = a >= b;
   8 assign ges = $signed(a) >= $signed(b);
   9 assign leu = a <= b;
  10 assign les = $signed(a) <= $signed(b);
  11 endmodule
  12 EOT
  13
  14 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6
  15 design -load postopt
  16 select -assert-count 8 t:$lcu r:WIDTH=5 %i
  17 select -assert-none t:$gt t:$ge t:$lt t:$le
  18
  19 design -load preopt
  20 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4
  21 design -load postopt
  22 select -assert-count 8 t:$lcu r:WIDTH=7 %i
  23 select -assert-none t:$gt t:$ge t:$lt t:$le
  24
  25
  26 design -reset
  27 read_verilog <<EOT
  28 module top(input [8:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
  29 wire [13:0] c = {a[8:6], 3'b101, a[5:4], 2'b11, a[3:0]};
  30 wire [13:0] d = {b[8], 3'b101, b[7:4], 2'b01, b[3:0]};
  31 assign gtu = c > d;
  32 assign gts = $signed(c) > $signed(d);
  33 assign ltu = c < d;
  34 assign lts = $signed(c) < $signed(d);
  35 assign geu = c >= d;
  36 assign ges = $signed(c) >= $signed(d);
  37 assign leu = c <= d;
  38 assign les = $signed(c) <= $signed(d);
  39 endmodule
  40 EOT
  41 design -save gold
  42
  43 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5
  44 design -load postopt
  45 select -assert-count 8 t:$lcu r:WIDTH=2 %i
  46 select -assert-none t:$gt t:$ge t:$lt t:$le
  47
  48 design -load preopt
  49 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3
  50 design -load postopt
  51 select -assert-count 8 t:$lcu r:WIDTH=4 %i
  52 select -assert-none t:$gt t:$ge t:$lt t:$le