tests/techmap/dff2dffs.ys

   1 read_verilog << EOT
   2 module top(...);
   3 input clk;
   4 input d;
   5 input sr;
   6 output reg q0, q1, q2, q3, q4, q5;
   7
   8 initial q0 = 1'b0;
   9 initial q1 = 1'b0;
  10 initial q2 = 1'b1;
  11 initial q3 = 1'b1;
  12 initial q4 = 1'bx;
  13 initial q5 = 1'bx;
  14
  15 always @(posedge clk) begin
  16         q0 <= sr ? 1'b0 : d;
  17         q1 <= sr ? 1'b1 : d;
  18         q2 <= sr ? 1'b0 : d;
  19         q3 <= sr ? 1'b1 : d;
  20         q4 <= sr ? 1'b0 : d;
  21         q5 <= sr ? 1'b1 : d;
  22 end
  23
  24 endmodule
  25 EOT
  26
  27 proc
  28 simplemap
  29 design -save ref
  30
  31 dff2dffs
  32 clean
  33
  34 select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
  35 select -assert-count 1 w:q1 %x t:$__DFFS_PP1_ %i
  36 select -assert-count 1 w:q2 %x t:$__DFFS_PP0_ %i
  37 select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
  38 select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
  39 select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
  40
  41 design -load ref
  42 dff2dffs -match-init
  43 clean
  44
  45 select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
  46 select -assert-count 0 w:q1 %x t:$__DFFS_PP1_ %i
  47 select -assert-count 0 w:q2 %x t:$__DFFS_PP0_ %i
  48 select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
  49 select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
  50 select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i