tests/techmap/dff2ff.ys

   1 read_verilog -icells << EOT
   2 module top(...);
   3
   4 input [1:0] D;
   5 input C;
   6 output [1:0] Q;
   7
   8 always @(posedge C)
   9   Q <= D;
  10
  11 endmodule
  12 EOT
  13
  14 proc
  15
  16 equiv_opt techmap -map +/dff2ff.v