tests/techmap/dfflegalize_adlatch.ys

   1 read_verilog -icells <<EOT
   2
   3 module adlatch0(input E, R, D, output [2:0] Q);
   4 $_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
   5 $_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
   6 $_DLATCH_NP0_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
   7 endmodule
   8
   9 module adlatch1(input E, R, D, output [2:0] Q);
  10 $_DLATCH_PP1_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
  11 $_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
  12 $_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
  13 endmodule
  14
  15 module top(input C, E, R, D, output [13:0] Q);
  16 adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0]));
  17 adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3]));
  18 endmodule
  19
  20 EOT
  21
  22 design -save orig
  23 flatten
  24 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
  25 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
  26
  27
  28 # Convert everything to ADLATCHs.
  29
  30 design -load orig
  31 dfflegalize -cell $_DLATCH_PP0_ x
  32
  33 select -assert-count 2 adlatch0/t:$_NOT_
  34 select -assert-count 8 adlatch1/t:$_NOT_
  35 select -assert-count 0 adlatch0/t:$_MUX_
  36 select -assert-count 0 adlatch1/t:$_MUX_
  37 select -assert-count 6 t:$_DLATCH_PP0_
  38 select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
  39
  40
  41 # Convert everything to DLATCHSRs.
  42
  43 design -load orig
  44 dfflegalize -cell $_DLATCHSR_PPP_ x
  45
  46 select -assert-count 2 adlatch0/t:$_NOT_
  47 select -assert-count 2 adlatch1/t:$_NOT_
  48 select -assert-count 0 adlatch0/t:$_MUX_
  49 select -assert-count 0 adlatch1/t:$_MUX_
  50 select -assert-count 6 t:$_DLATCHSR_PPP_
  51 select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i