tests/techmap/dfflegalize_dlatch.ys

   1 read_verilog -icells <<EOT
   2
   3 module dlatch(input E, D, output [1:0] Q);
   4 $_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0]));
   5 $_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1]));
   6 endmodule
   7
   8 EOT
   9
  10 design -save orig
  11 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
  12 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
  13 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
  14 equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
  15 equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
  16
  17 # Convert everything to DFFs.
  18
  19 design -load orig
  20 dfflegalize -cell $_DLATCH_P_ x
  21
  22 select -assert-count 1 t:$_NOT_
  23 select -assert-count 2 t:$_DLATCH_P_
  24 select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i
  25
  26
  27 # Convert everything to ADLATCHs.
  28
  29 design -load orig
  30 dfflegalize -cell $_DLATCH_PP0_ x
  31
  32 select -assert-count 1 t:$_NOT_
  33 select -assert-count 2 t:$_DLATCH_PP0_
  34 select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
  35
  36
  37 # Convert everything to DLATCHSRs.
  38
  39 design -load orig
  40 dfflegalize -cell $_DLATCHSR_PPP_ x
  41
  42 select -assert-count 1 t:$_NOT_
  43 select -assert-count 2 t:$_DLATCHSR_PPP_
  44 select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
  45
  46
  47 # Convert everything to ALDFFs.
  48
  49 design -load orig
  50 dfflegalize -cell $_ALDFF_PP_ x
  51
  52 select -assert-count 1 t:$_NOT_
  53 select -assert-count 2 t:$_ALDFF_PP_
  54 select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i
  55
  56
  57 # Convert everything to ALDFFEs.
  58
  59 design -load orig
  60 dfflegalize -cell $_ALDFFE_PPP_ x
  61
  62 select -assert-count 1 t:$_NOT_
  63 select -assert-count 2 t:$_ALDFFE_PPP_
  64 select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i