tests/techmap/dfflegalize_dlatch_const.ys

   1 read_verilog -icells <<EOT
   2
   3 module dlatch(input E, D, (* init = 8'hf0 *) output [7:0] Q);
   4 $_DLATCH_P_ ff0 (.E(E), .D(1'b0), .Q(Q[0]));
   5 $_DLATCH_N_ ff1 (.E(E), .D(1'b0), .Q(Q[1]));
   6 $_DLATCH_P_ ff2 (.E(E), .D(1'b1), .Q(Q[2]));
   7 $_DLATCH_N_ ff3 (.E(E), .D(1'b1), .Q(Q[3]));
   8 $_DLATCH_P_ ff4 (.E(E), .D(1'b0), .Q(Q[4]));
   9 $_DLATCH_N_ ff5 (.E(E), .D(1'b0), .Q(Q[5]));
  10 $_DLATCH_P_ ff6 (.E(E), .D(1'b1), .Q(Q[6]));
  11 $_DLATCH_N_ ff7 (.E(E), .D(1'b1), .Q(Q[7]));
  12 endmodule
  13
  14 EOT
  15
  16 design -save orig
  17 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01
  18 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0
  19 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
  20 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
  21
  22 # Convert everything to ADFFs.
  23
  24 design -load orig
  25 dfflegalize -cell $_DFF_PP0_ 01
  26
  27 select -assert-count 12 t:$_NOT_
  28 select -assert-count 8 t:$_DFF_PP0_
  29 select -assert-none t:$_DFF_PP0_ t:$_NOT_ %% %n t:* %i
  30
  31 design -load orig
  32 dfflegalize -cell $_DFF_PP?_ 0
  33
  34 select -assert-count 12 t:$_NOT_
  35 select -assert-count 4 t:$_DFF_PP0_
  36 select -assert-count 4 t:$_DFF_PP1_
  37 select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i
  38
  39 # Convert everything to DFFSREs.
  40
  41 design -load orig
  42 dfflegalize -cell $_DFFSRE_PPPP_ 0
  43
  44 select -assert-count 12 t:$_NOT_
  45 select -assert-count 8 t:$_DFFSRE_PPPP_
  46 select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i
  47
  48 design -load orig
  49 dfflegalize -cell $_DFFSRE_PPPP_ 1
  50
  51 select -assert-count 12 t:$_NOT_
  52 select -assert-count 8 t:$_DFFSRE_PPPP_
  53 select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i