tests/techmap/dfflegalize_dlatch_init.ys

   1 read_verilog -icells <<EOT
   2
   3 module dlatch(input E, D, (* init = 2'h0 *) output [1:0] Q);
   4 $_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0]));
   5 $_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1]));
   6 endmodule
   7
   8 EOT
   9
  10 design -save orig
  11 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0
  12 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1
  13 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
  14 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
  15 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
  16 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
  17 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
  18 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
  19
  20 # Convert everything to DFFs.
  21
  22 design -load orig
  23 dfflegalize -cell $_DLATCH_P_ 0
  24
  25 select -assert-count 1 t:$_NOT_
  26 select -assert-count 2 t:$_DLATCH_P_
  27 select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i
  28
  29 design -load orig
  30 dfflegalize -cell $_DLATCH_P_ 1
  31
  32 select -assert-count 5 t:$_NOT_
  33 select -assert-count 2 t:$_DLATCH_P_
  34 select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i
  35
  36
  37 # Convert everything to ADLATCHs.
  38
  39 design -load orig
  40 dfflegalize -cell $_DLATCH_PP0_ 0
  41
  42 select -assert-count 1 t:$_NOT_
  43 select -assert-count 2 t:$_DLATCH_PP0_
  44 select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
  45
  46 design -load orig
  47 dfflegalize -cell $_DLATCH_PP0_ 1
  48
  49 select -assert-count 5 t:$_NOT_
  50 select -assert-count 2 t:$_DLATCH_PP0_
  51 select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
  52
  53 design -load orig
  54 dfflegalize -cell $_DLATCH_PP1_ 0
  55
  56 select -assert-count 1 t:$_NOT_
  57 select -assert-count 2 t:$_DLATCH_PP1_
  58 select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i
  59
  60 design -load orig
  61 dfflegalize -cell $_DLATCH_PP1_ 1
  62
  63 select -assert-count 5 t:$_NOT_
  64 select -assert-count 2 t:$_DLATCH_PP1_
  65 select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i
  66
  67
  68 # Convert everything to DLATCHSRs.
  69
  70 design -load orig
  71 dfflegalize -cell $_DLATCHSR_PPP_ 0
  72
  73 select -assert-count 1 t:$_NOT_
  74 select -assert-count 2 t:$_DLATCHSR_PPP_
  75 select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
  76
  77 design -load orig
  78 dfflegalize -cell $_DLATCHSR_PPP_ 1
  79
  80 select -assert-count 5 t:$_NOT_
  81 select -assert-count 2 t:$_DLATCHSR_PPP_
  82 select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i