tests/techmap/extractinv.ys

   1 read_verilog << EOT
   2
   3 module ff4(...);
   4 parameter [0:0] CLK_INV = 1'b0;
   5 parameter [3:0] DATA_INV = 4'b0000;
   6 (* invertible_pin = "CLK_INV" *)
   7 input clk;
   8 (* invertible_pin = "DATA_INV" *)
   9 input [3:0] d;
  10 output [3:0] q;
  11 endmodule
  12
  13 module inv(...);
  14 output o;
  15 input i;
  16 endmodule
  17
  18 module top(...);
  19 input d0, d1, d2, d3;
  20 input clk;
  21 output q;
  22 ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q));
  23 endmodule
  24
  25 EOT
  26
  27 extractinv -inv inv o:i
  28 clean
  29
  30 select -assert-count 2 top/t:inv
  31 select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i
  32
  33 select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i
  34 select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i
  35 select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i
  36 select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i
  37
  38 select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i
  39 select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i
  40 select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i
  41 select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i