tests/techmap/mem_simple_4x1_cells.v

   1 module MEM4X1 (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
   2         input CLK, WR_DATA, WR_EN;
   3         input [3:0] RD_ADDR, WR_ADDR;
   4         output reg RD_DATA;
   5
   6         reg [15:0] memory;
   7
   8         always @(posedge CLK) begin
   9                 if (WR_EN)
  10                         memory[WR_ADDR] <= WR_DATA;
  11                 RD_DATA <= memory[RD_ADDR];
  12         end
  13 endmodule