5 ..
/..
/yosys
-b 'verilog -noattr' -o mem_simple_4x1_synth.v
-p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
7 iverilog
-o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
8 iverilog
-o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v
10 .
/mem_simple_4x1_gold_tb
> mem_simple_4x1_gold_tb.out
11 .
/mem_simple_4x1_gate_tb
> mem_simple_4x1_gate_tb.out
13 diff -u mem_simple_4x1_gold_tb.out mem_simple_4x1_gate_tb.out
14 rm -f mem_simple_4x1_synth.v mem_simple_4x1_tb.vcd
15 rm -f mem_simple_4x1_
{gold
,gate
}_tb
{,.out
}