fail svinterfaces testcases on yosys error exit
[yosys.git] / tests / techmap / mem_simple_4x1_tb.v
1 module tb;
2
3 reg clk, rst;
4 wire [7:0] out;
5 wire [4:0] counter;
6
7 uut uut (clk, rst, out, counter);
8
9 initial begin
10 #5 clk <= 0;
11 repeat (100) #5 clk <= ~clk;
12 #5 $finish;
13 end
14
15 initial begin
16 rst <= 1;
17 repeat (2) @(posedge clk);
18 rst <= 0;
19 end
20
21 always @(posedge clk)
22 $display("%d %d %d", rst, out, counter);
23
24 initial begin
25 $dumpfile("mem_simple_4x1_tb.vcd");
26 $dumpvars(0, uut);
27 end
28
29 endmodule