tests/techmap/mem_simple_4x1_uut.v

   1 module uut (clk, rst, out, counter);
   2
   3 input clk, rst;
   4 output reg [7:0] out;
   5 output reg [4:0] counter;
   6
   7 reg [7:0] memory [0:19];
   8
   9 always @(posedge clk) begin
  10         counter <= rst || counter == 19 ? 0 : counter+1;
  11         memory[counter] <= counter;
  12         out <= memory[counter];
  13 end
  14
  15 endmodule