tests/techmap/shiftx2mux.ys

   1 read_verilog <<EOT
   2 module sc1 (i1 ,
   3             i2 ,
   4             i3 ,
   5             i4 ,
   6             i5 ,
   7             i6 ,
   8             i7 ,
   9             i8 ,
  10             i9 ,
  11             i10,
  12             i11,
  13             i12,
  14             i13,
  15             i14,
  16             i15,
  17             binary_out,
  18             encoder_in,
  19             enable
  20 );
  21
  22 input [3:0]   i1 ;
  23 input [3:0]   i2 ;
  24 input [3:0]   i3 ;
  25 input [3:0]   i4 ;
  26 input [3:0]   i5 ;
  27 input [3:0]   i6 ;
  28 input [3:0]   i7 ;
  29 input [3:0]   i8 ;
  30 input [3:0]   i9 ;
  31 input [3:0]   i10 ;
  32 input [3:0]   i11 ;
  33 input [3:0]   i12 ;
  34 input [3:0]   i13 ;
  35 input [3:0]   i14 ;
  36 input [3:0]   i15 ;
  37
  38 output reg [3:0] binary_out  ;
  39
  40 input [3:0] encoder_in ;
  41 input  enable ;
  42
  43
  44
  45 always @ (*)
  46 begin
  47         binary_out = 0;
  48         if (enable) begin
  49                 case (encoder_in)
  50                         4'h1 : binary_out = i1;
  51                         4'h2 : binary_out = i2;
  52                         4'h3 : binary_out = i3;
  53                         4'h4 : binary_out = i4;
  54                         4'h5 : binary_out = i5;
  55                         4'h6 : binary_out = i6;
  56                         4'h7 : binary_out = i7;
  57                         4'h8 : binary_out = i8;
  58                         4'h9 : binary_out = i9;
  59                         4'ha : binary_out = i10;
  60                         4'hb : binary_out = i11;/*
  61                         4'hc : binary_out = i12;
  62                         4'hd : binary_out = i13;
  63                         4'he : binary_out = i14;
  64                         4'hf : binary_out = i15;*/
  65                endcase
  66        end
  67 end
  68 endmodule
  69 EOT
  70
  71 proc
  72 pmux2shiftx
  73 design -save gold
  74
  75
  76 design -load gold
  77 techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
  78 abc -lut 6
  79 select -assert-min 17 t:$lut
  80
  81
  82 design -load gold
  83 techmap
  84 abc -lut 6
  85 select -assert-count 16 t:$lut
  86
  87 design -stash gate
  88 design -import gold -as gold
  89 design -import gate -as gate
  90 miter -equiv -flatten -make_assert -make_outputs gold gate miter
  91 sat -verify -prove-asserts -show-ports miter
  92
  93
  94 design -load gold
  95 techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
  96 abc9 -lut 6
  97 select -assert-min 17 t:$lut
  98
  99
 100 design -load gold
 101 techmap
 102 abc9 -lut 6
 103 select -assert-count 16 t:$lut
 104
 105 design -stash gate
 106 design -import gold -as gold
 107 design -import gate -as gate
 108 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 109 sat -verify -prove-asserts -show-ports miter
 110
 111
 112 design -reset
 113 read_verilog <<EOT
 114 module top(input [6:0] A, input [1:0] B, output [1:0] Y);
 115 wire [7:0] AA = {1'bx, A};
 116 assign Y = AA[B*2 +: 2];
 117 endmodule
 118 EOT
 119 opt
 120 wreduce
 121 equiv_opt techmap