38 output reg [3:0] binary_out ;
40 input [3:0] encoder_in ;
50 4'h1 : binary_out = i1;
51 4'h2 : binary_out = i2;
52 4'h3 : binary_out = i3;
53 4'h4 : binary_out = i4;
54 4'h5 : binary_out = i5;
55 4'h6 : binary_out = i6;
56 4'h7 : binary_out = i7;
57 4'h8 : binary_out = i8;
58 4'h9 : binary_out = i9;
59 4'ha : binary_out = i10;
60 4'hb : binary_out = i11;/*
61 4'hc : binary_out = i12;
62 4'hd : binary_out = i13;
63 4'he : binary_out = i14;
64 4'hf : binary_out = i15;*/
79 select -assert-count 16 t:$lut
82 design -import gold -as gold
83 design -import gate -as gate
84 miter -equiv -flatten -make_assert -make_outputs gold gate miter
85 sat -verify -prove-asserts -show-ports miter
91 select -assert-count 16 t:$lut
94 design -import gold -as gold
95 design -import gate -as gate
96 miter -equiv -flatten -make_assert -make_outputs gold gate miter
97 sat -verify -prove-asserts -show-ports miter
102 module top(input [6:0] A, input [1:0] B, output [1:0] Y);
103 wire [7:0] AA = {1'bx, A};
104 assign Y = AA[B*2 +: 2];