tests/techmap/techmap_replace.ys

   1 read_verilog <<EOT
   2 module sub(input i, output o, input j);
   3 foobar _TECHMAP_REPLACE_(i, o, j);
   4 wire _TECHMAP_REPLACE_.asdf = i ;
   5 barfoo _TECHMAP_REPLACE_.blah (i, o, j);
   6 endmodule
   7 EOT
   8 design -stash techmap
   9
  10 read_verilog <<EOT
  11 module top(input i, output o);
  12 sub s0(i, o);
  13 endmodule
  14 EOT
  15
  16 techmap -map %techmap
  17 select -assert-any w:s0.asdf
  18 select -assert-any c:s0.blah