tests/techmap/wireinit.ys

   1 read_verilog <<EOT
   2 (* techmap_celltype = "$_DFF_P_" *)
   3 module ffmap(...);
   4 input D;
   5 input C;
   6 output Q;
   7 parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
   8
   9 ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
  10
  11 wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
  12
  13 wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
  14
  15 endmodule
  16 EOT
  17 design -stash map
  18
  19 read_verilog <<EOT
  20 (* techmap_celltype = "$_DFF_P_" *)
  21 module ffmap(...);
  22 input D;
  23 input C;
  24 output Q;
  25 parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
  26
  27 ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
  28
  29 wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
  30
  31 wire _TECHMAP_REMOVEINIT_Q_ = 1'b0;
  32
  33 endmodule
  34 EOT
  35 design -stash map_noremove
  36
  37 read_verilog <<EOT
  38 module ffbb (...);
  39 parameter [0:0] INIT = 1'bx;
  40 input D, C;
  41 output Q;
  42 endmodule
  43
  44 module top(...);
  45 input clk;
  46 input d;
  47 output reg q0 = 0;
  48 output reg q1 = 1;
  49 output reg qq0 = 0;
  50 output reg qx;
  51
  52 always @(posedge clk) begin
  53         q0 <= d;
  54         q1 <= d;
  55         qq0 <= q0;
  56         qx <= d;
  57 end
  58 endmodule
  59 EOT
  60
  61 design -save ref
  62
  63 hierarchy -auto-top
  64 proc
  65 simplemap
  66 techmap -map %map
  67 clean
  68 # Make sure the parameter was used properly.
  69 select -assert-count 3 top/t:ffbb
  70 select -set ff0 top/w:q0 %ci t:ffbb %i
  71 select -set ffq0 top/w:qq0 %ci t:ffbb %i
  72 select -set ffx top/w:qx %ci t:ffbb %i
  73 select -assert-count 1 @ff0
  74 select -assert-count 1 @ffq0
  75 select -assert-count 1 @ffx
  76 select -assert-count 1 @ff0 r:INIT=1'b0 %i
  77 select -assert-count 1 @ffq0 r:INIT=1'b0 %i
  78 select -assert-count 1 @ffx r:INIT=1'bx %i
  79 select -assert-count 0 top/w:q1 %ci t:ffbb %i
  80 # Make sure the init values are dropped from the wires iff mapping was performed.
  81 select -assert-count 0 top/w:q0 a:init %i
  82 select -assert-count 0 top/w:qq0 a:init %i
  83 select -assert-count 1 top/w:q1 a:init=1'b1 %i
  84 select -assert-count 0 top/w:qx a:init %i
  85
  86 design -load ref
  87 hierarchy -auto-top
  88 proc
  89 simplemap
  90 techmap -map %map_noremove
  91 clean
  92 # Make sure the parameter was used properly.
  93 select -assert-count 3 top/t:ffbb
  94 select -set ff0 top/w:q0 %ci t:ffbb %i
  95 select -set ffq0 top/w:qq0 %ci t:ffbb %i
  96 select -set ffx top/w:qx %ci t:ffbb %i
  97 select -assert-count 1 @ff0
  98 select -assert-count 1 @ffq0
  99 select -assert-count 1 @ffx
 100 select -assert-count 1 @ff0 r:INIT=1'b0 %i
 101 select -assert-count 1 @ffq0 r:INIT=1'b0 %i
 102 select -assert-count 1 @ffx r:INIT=1'bx %i
 103 select -assert-count 0 top/w:q1 %ci t:ffbb %i
 104 # Make sure the init values are not dropped from the wires.
 105 select -assert-count 1 top/w:q0 a:init=1'b0 %i
 106 select -assert-count 1 top/w:qq0 a:init=1'b0 %i
 107 select -assert-count 1 top/w:q1 a:init=1'b1 %i
 108 select -assert-count 0 top/w:qx a:init %i