tests/techmap/zinit.ys

   1 read_verilog -icells <<EOT
   2 module top(input C, R, input [1:0] D, (* init = {2'b10, 2'b01, 1'b1, {8{1'b1}}} *) output [12:0] Q);
   3
   4 (* init = 1'b1 *)
   5 wire unused;
   6
   7 $_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
   8 $_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
   9 $_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
  10 $_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
  11 $_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
  12 $_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
  13 $_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
  14 $_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
  15
  16 $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
  17 $adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
  18 endmodule
  19 EOT
  20 equiv_opt -assert -multiclock zinit
  21 design -load postopt
  22
  23 select -assert-count 16 t:$_NOT_
  24 select -assert-count 4 t:$xor
  25 select -assert-count 1 w:unused a:init %i
  26 select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
  27 select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??1_ %i
  28 select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??0_ %i
  29
  30
  31 design -reset
  32 read_verilog -icells <<EOT
  33 module top(input C, R, input [1:0] D, (* init = {2'bx0, 2'b0x, 1'b1, {8{1'b0}}} *) output [12:0] Q);
  34
  35 (* init = 1'b1 *)
  36 wire unused;
  37
  38 $_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
  39 $_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
  40 $_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
  41 $_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
  42 $_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
  43 $_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
  44 $_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
  45 $_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
  46
  47 $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
  48 $adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
  49 endmodule
  50 EOT
  51 equiv_opt -assert -multiclock zinit
  52 design -load postopt
  53
  54 select -assert-count 0 t:$_NOT_
  55 select -assert-count 1 w:unused a:init %i
  56 select -assert-count 1 w:Q a:init=13'bx00x100000000 %i
  57 select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??0_ %i
  58 select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??1_ %i
  59
  60
  61 design -reset
  62 read_verilog -icells <<EOT
  63 module top(input C, R, D, E, (* init = {24{1'b1}} *) output [23:0] Q);
  64
  65 $_DFFE_NN0P_ dff0 (.C(C), .D(D), .E(E), .R(R), .Q(Q[0]));
  66 $_DFFE_NN1P_ dff1 (.C(C), .D(D), .E(E), .R(R), .Q(Q[1]));
  67 $_DFFE_NP0P_ dff2 (.C(C), .D(D), .E(E), .R(R), .Q(Q[2]));
  68 $_DFFE_NP1P_ dff3 (.C(C), .D(D), .E(E), .R(R), .Q(Q[3]));
  69 $_DFFE_PN0P_ dff4 (.C(C), .D(D), .E(E), .R(R), .Q(Q[4]));
  70 $_DFFE_PN1P_ dff5 (.C(C), .D(D), .E(E), .R(R), .Q(Q[5]));
  71 $_DFFE_PP0P_ dff6 (.C(C), .D(D), .E(E), .R(R), .Q(Q[6]));
  72 $_DFFE_PP1P_ dff7 (.C(C), .D(D), .E(E), .R(R), .Q(Q[7]));
  73
  74 $_SDFF_NN0_ dff8 (.C(C), .D(D[0]), .R(R), .Q(Q[8]));
  75 $_SDFF_NN1_ dff9 (.C(C), .D(D[0]), .R(R), .Q(Q[9]));
  76 $_SDFF_NP0_ dff10(.C(C), .D(D[0]), .R(R), .Q(Q[10]));
  77 $_SDFF_NP1_ dff11(.C(C), .D(D[0]), .R(R), .Q(Q[11]));
  78 $_SDFF_PN0_ dff12(.C(C), .D(D[0]), .R(R), .Q(Q[12]));
  79 $_SDFF_PN1_ dff13(.C(C), .D(D[0]), .R(R), .Q(Q[13]));
  80 $_SDFF_PP0_ dff14(.C(C), .D(D[0]), .R(R), .Q(Q[14]));
  81 $_SDFF_PP1_ dff15(.C(C), .D(D[0]), .R(R), .Q(Q[15]));
  82
  83 $_SDFFE_NN0P_ dff16(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[16]));
  84 $_SDFFE_NN1P_ dff17(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[17]));
  85 $_SDFFE_NP0P_ dff18(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[18]));
  86 $_SDFFE_NP1P_ dff19(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[19]));
  87 $_SDFFE_PN0P_ dff20(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[20]));
  88 $_SDFFE_PN1P_ dff21(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[21]));
  89 $_SDFFE_PP0P_ dff22(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[22]));
  90 $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[23]));
  91
  92 endmodule
  93 EOT
  94 #equiv_opt -assert -multiclock zinit
  95 #design -load postopt
  96 zinit
  97
  98 select -assert-count 48 t:$_NOT_
  99 select -assert-count 0 w:Q a:init %i
 100 select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFFE_??1P_ %i
 101 select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFFE_??0P_ %i
 102 select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$_SDFF_??1_ %i
 103 select -assert-count 4 c:dff9 c:dff11 c:dff13 c:dff15 %% t:$_SDFF_??0_ %i
 104 select -assert-count 4 c:dff16 c:dff18 c:dff20 c:dff22 %% t:$_SDFFE_??1P_ %i
 105 select -assert-count 4 c:dff17 c:dff19 c:dff21 c:dff23 %% t:$_SDFFE_??0P_ %i
 106
 107
 108 design -reset
 109 read_verilog -icells <<EOT
 110 module top(input C, R, D, E, (* init = {24{1'b0}} *) output [23:0] Q);
 111
 112 $_DFFE_NN0P_ dff0 (.C(C), .D(D), .E(E), .R(R), .Q(Q[0]));
 113 $_DFFE_NN1P_ dff1 (.C(C), .D(D), .E(E), .R(R), .Q(Q[1]));
 114 $_DFFE_NP0P_ dff2 (.C(C), .D(D), .E(E), .R(R), .Q(Q[2]));
 115 $_DFFE_NP1P_ dff3 (.C(C), .D(D), .E(E), .R(R), .Q(Q[3]));
 116 $_DFFE_PN0P_ dff4 (.C(C), .D(D), .E(E), .R(R), .Q(Q[4]));
 117 $_DFFE_PN1P_ dff5 (.C(C), .D(D), .E(E), .R(R), .Q(Q[5]));
 118 $_DFFE_PP0P_ dff6 (.C(C), .D(D), .E(E), .R(R), .Q(Q[6]));
 119 $_DFFE_PP1P_ dff7 (.C(C), .D(D), .E(E), .R(R), .Q(Q[7]));
 120
 121 $_SDFF_NN0_ dff8 (.C(C), .D(D[0]), .R(R), .Q(Q[8]));
 122 $_SDFF_NN1_ dff9 (.C(C), .D(D[0]), .R(R), .Q(Q[9]));
 123 $_SDFF_NP0_ dff10(.C(C), .D(D[0]), .R(R), .Q(Q[10]));
 124 $_SDFF_NP1_ dff11(.C(C), .D(D[0]), .R(R), .Q(Q[11]));
 125 $_SDFF_PN0_ dff12(.C(C), .D(D[0]), .R(R), .Q(Q[12]));
 126 $_SDFF_PN1_ dff13(.C(C), .D(D[0]), .R(R), .Q(Q[13]));
 127 $_SDFF_PP0_ dff14(.C(C), .D(D[0]), .R(R), .Q(Q[14]));
 128 $_SDFF_PP1_ dff15(.C(C), .D(D[0]), .R(R), .Q(Q[15]));
 129
 130 $_SDFFE_NN0P_ dff16(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[16]));
 131 $_SDFFE_NN1P_ dff17(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[17]));
 132 $_SDFFE_NP0P_ dff18(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[18]));
 133 $_SDFFE_NP1P_ dff19(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[19]));
 134 $_SDFFE_PN0P_ dff20(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[20]));
 135 $_SDFFE_PN1P_ dff21(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[21]));
 136 $_SDFFE_PP0P_ dff22(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[22]));
 137 $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[23]));
 138
 139 endmodule
 140 EOT
 141 #equiv_opt -assert -multiclock zinit
 142 #design -load postopt
 143 zinit
 144
 145 select -assert-count 0 t:$_NOT_
 146 select -assert-count 1 w:Q a:init=24'b0 %i
 147 select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFFE_??0P_ %i
 148 select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFFE_??1P_ %i
 149 select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$_SDFF_??0_ %i
 150 select -assert-count 4 c:dff9 c:dff11 c:dff13 c:dff15 %% t:$_SDFF_??1_ %i
 151 select -assert-count 4 c:dff16 c:dff18 c:dff20 c:dff22 %% t:$_SDFFE_??0P_ %i
 152 select -assert-count 4 c:dff17 c:dff19 c:dff21 c:dff23 %% t:$_SDFFE_??1P_ %i