tests/test_lib_scheduler.py

   1 # nmigen: UnusedElaboratable=no
   2
   3 import unittest
   4
   5 from nmigen.hdl import *
   6 from nmigen.asserts import *
   7 from nmigen.sim import *
   8 from nmigen.lib.scheduler import *
   9
  10 from .utils import *
  11
  12
  13 class RoundRobinTestCase(unittest.TestCase):
  14     def test_count(self):
  15         dut = RoundRobin(count=32)
  16         self.assertEqual(dut.count, 32)
  17         self.assertEqual(len(dut.requests), 32)
  18         self.assertEqual(len(dut.grant), 5)
  19
  20     def test_wrong_count(self):
  21         with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not 'foo'"):
  22             dut = RoundRobin(count="foo")
  23         with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not -1"):
  24             dut = RoundRobin(count=-1)
  25
  26
  27 class RoundRobinSimulationTestCase(unittest.TestCase):
  28     def test_count_one(self):
  29         dut = RoundRobin(count=1)
  30         sim = Simulator(dut)
  31         def process():
  32             yield dut.requests.eq(0)
  33             yield; yield Delay(1e-8)
  34             self.assertEqual((yield dut.grant), 0)
  35             self.assertFalse((yield dut.valid))
  36
  37             yield dut.requests.eq(1)
  38             yield; yield Delay(1e-8)
  39             self.assertEqual((yield dut.grant), 0)
  40             self.assertTrue((yield dut.valid))
  41         sim.add_sync_process(process)
  42         sim.add_clock(1e-6)
  43         with sim.write_vcd("test.vcd"):
  44             sim.run()
  45
  46     def test_transitions(self):
  47         dut = RoundRobin(count=3)
  48         sim = Simulator(dut)
  49         def process():
  50             yield dut.requests.eq(0b111)
  51             yield; yield Delay(1e-8)
  52             self.assertEqual((yield dut.grant), 1)
  53             self.assertTrue((yield dut.valid))
  54
  55             yield dut.requests.eq(0b110)
  56             yield; yield Delay(1e-8)
  57             self.assertEqual((yield dut.grant), 2)
  58             self.assertTrue((yield dut.valid))
  59
  60             yield dut.requests.eq(0b010)
  61             yield; yield Delay(1e-8)
  62             self.assertEqual((yield dut.grant), 1)
  63             self.assertTrue((yield dut.valid))
  64
  65             yield dut.requests.eq(0b011)
  66             yield; yield Delay(1e-8)
  67             self.assertEqual((yield dut.grant), 0)
  68             self.assertTrue((yield dut.valid))
  69
  70             yield dut.requests.eq(0b001)
  71             yield; yield Delay(1e-8)
  72             self.assertEqual((yield dut.grant), 0)
  73             self.assertTrue((yield dut.valid))
  74
  75             yield dut.requests.eq(0b101)
  76             yield; yield Delay(1e-8)
  77             self.assertEqual((yield dut.grant), 2)
  78             self.assertTrue((yield dut.valid))
  79
  80             yield dut.requests.eq(0b100)
  81             yield; yield Delay(1e-8)
  82             self.assertEqual((yield dut.grant), 2)
  83             self.assertTrue((yield dut.valid))
  84
  85             yield dut.requests.eq(0b000)
  86             yield; yield Delay(1e-8)
  87             self.assertFalse((yield dut.valid))
  88
  89             yield dut.requests.eq(0b001)
  90             yield; yield Delay(1e-8)
  91             self.assertEqual((yield dut.grant), 0)
  92             self.assertTrue((yield dut.valid))
  93         sim.add_sync_process(process)
  94         sim.add_clock(1e-6)
  95         with sim.write_vcd("test.vcd"):
  96             sim.run()