Merge remote-tracking branch 'origin/master' into eddie/muxpack
[yosys.git] / tests / tools / autotest.sh
1 #!/usr/bin/env bash
2
3 libs=""
4 genvcd=false
5 use_xsim=false
6 use_modelsim=false
7 verbose=false
8 keeprunning=false
9 makejmode=false
10 frontend="verilog -noblackbox"
11 backend_opts="-noattr -noexpr -siminit"
12 autotb_opts=""
13 include_opts=""
14 xinclude_opts=""
15 minclude_opts=""
16 scriptfiles=""
17 scriptopt=""
18 toolsdir="$(cd $(dirname $0); pwd)"
19 warn_iverilog_git=false
20 # The following are used in verilog to firrtl regression tests.
21 # Typically these will be passed as environment variables:
22 #EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
23 # The tests are skipped if firrtl2verilog is the empty string (the default).
24 firrtl2verilog=""
25 xfirrtl="../xfirrtl"
26
27 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
28 ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
29 fi
30
31 while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
32 case "$opt" in
33 x)
34 use_xsim=true ;;
35 m)
36 use_modelsim=true ;;
37 G)
38 warn_iverilog_git=true ;;
39 l)
40 libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
41 w)
42 genvcd=true ;;
43 k)
44 keeprunning=true ;;
45 j)
46 makejmode=true ;;
47 v)
48 verbose=true ;;
49 r)
50 backend_opts="$backend_opts -norename" ;;
51 e)
52 backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
53 f)
54 frontend="$OPTARG" ;;
55 s)
56 [[ "$OPTARG" == /* ]] || OPTARG="$PWD/$OPTARG"
57 scriptfiles="$scriptfiles $OPTARG" ;;
58 p)
59 scriptopt="$OPTARG" ;;
60 n)
61 autotb_opts="$autotb_opts -n $OPTARG" ;;
62 S)
63 autotb_opts="$autotb_opts -seed $OPTARG" ;;
64 I)
65 include_opts="$include_opts -I $OPTARG"
66 xinclude_opts="$xinclude_opts -i $OPTARG"
67 minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
68 -)
69 case "${OPTARG}" in
70 xfirrtl)
71 xfirrtl="${!OPTIND}"
72 OPTIND=$(( $OPTIND + 1 ))
73 ;;
74 firrtl2verilog)
75 firrtl2verilog="${!OPTIND}"
76 OPTIND=$(( $OPTIND + 1 ))
77 ;;
78 *)
79 if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
80 echo "Unknown option --${OPTARG}" >&2
81 fi
82 ;;
83 esac;;
84 *)
85 echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
86 exit 1
87 esac
88 done
89
90 compile_and_run() {
91 exe="$1"; output="$2"; shift 2
92 ext=${1##*.}
93 if [ "$ext" == "sv" ]; then
94 language_gen="-g2012"
95 else
96 language_gen="-g2005"
97 fi
98
99 if $use_modelsim; then
100 altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
101 /opt/altera/$altver/modelsim_ase/bin/vlib work
102 /opt/altera/$altver/modelsim_ase/bin/vlog $minclude_opts +define+outfile=\"$output\" "$@"
103 /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench
104 elif $use_xsim; then
105 xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; )
106 /opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
107 /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
108 else
109 iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
110 vvp -n "$exe"
111 fi
112 }
113
114 shift $((OPTIND - 1))
115
116 for fn
117 do
118 bn=${fn%.*}
119 ext=${fn##*.}
120 if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
121 echo "Invalid argument: $fn" >&2
122 exit 1
123 fi
124 [[ "$bn" == *_tb ]] && continue
125
126 if $makejmode; then
127 status_prefix="Test: $bn "
128 else
129 status_prefix=""
130 echo -n "Test: $bn "
131 fi
132
133 if [ "$ext" == sv ]; then
134 frontend="$frontend -sv"
135 fi
136
137 rm -f ${bn}.{err,log,skip}
138 mkdir -p ${bn}.out
139 rm -rf ${bn}.out/*
140
141 body() {
142 cd ${bn}.out
143 fn=$(basename $fn)
144 bn=$(basename $bn)
145
146 rm -f ${bn}_ref.fir
147 if [[ "$ext" == "v" ]]; then
148 egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
149 elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
150 "$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
151 else
152 cp ../${fn} ${bn}_ref.${ext}
153 fi
154
155 if [ ! -f ../${bn}_tb.v ]; then
156 "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
157 else
158 cp ../${bn}_tb.v ${bn}_tb.v
159 fi
160 if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
161 compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
162 "$toolsdir"/../../techlibs/common/simlib.v \
163 "$toolsdir"/../../techlibs/common/simcells.v
164 if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
165
166 test_count=0
167 test_passes() {
168 "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
169 compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
170 ${bn}_tb.v ${bn}_syn${test_count}.v $libs \
171 "$toolsdir"/../../techlibs/common/simlib.v \
172 "$toolsdir"/../../techlibs/common/simcells.v
173 if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
174 $toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
175 test_count=$(( test_count + 1 ))
176 }
177
178 if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.v; then
179 touch ../${bn}.skip
180 return
181 fi
182
183 if [ -n "$scriptfiles" ]; then
184 test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles
185 elif [ -n "$scriptopt" ]; then
186 test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
187 elif [ "$frontend" = "verific" ]; then
188 test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
189 elif [ "$frontend" = "verific_gates" ]; then
190 test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
191 else
192 test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
193 test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
194 if [ -n "$firrtl2verilog" ]; then
195 if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
196 "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
197 $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
198 test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
199 fi
200 fi
201 fi
202 touch ../${bn}.log
203 }
204
205 if $verbose; then
206 echo ".."
207 echo "Output written to console." > ${bn}.err
208 ( set -ex; body; )
209 else
210 ( set -ex; body; ) > ${bn}.err 2>&1
211 fi
212
213 did_firrtl=""
214 if [ -f ${bn}.out/${bn}_ref.fir ]; then
215 did_firrtl="+FIRRTL "
216 fi
217 if [ -f ${bn}.log ]; then
218 mv ${bn}.err ${bn}.log
219 echo "${status_prefix}${did_firrtl}-> ok"
220 elif [ -f ${bn}.skip ]; then
221 mv ${bn}.err ${bn}.skip
222 echo "${status_prefix}-> skip"
223 else
224 echo "${status_prefix}${did_firrtl}-> ERROR!"
225 if $warn_iverilog_git; then
226 echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
227 fi
228 $keeprunning || exit 1
229 fi
230 done
231
232 exit 0