opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests
[yosys.git] / tests / tools / autotest.sh
1 #!/usr/bin/env bash
2
3 libs=""
4 genvcd=false
5 use_xsim=false
6 use_modelsim=false
7 verbose=false
8 keeprunning=false
9 makejmode=false
10 frontend="verilog -noblackbox"
11 backend_opts="-noattr -noexpr -siminit"
12 autotb_opts=""
13 include_opts=""
14 xinclude_opts=""
15 minclude_opts=""
16 scriptfiles=""
17 scriptopt=""
18 toolsdir="$(cd $(dirname $0); pwd)"
19 warn_iverilog_git=false
20 # The following are used in verilog to firrtl regression tests.
21 # Typically these will be passed as environment variables:
22 #EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
23 # The tests are skipped if firrtl2verilog is the empty string (the default).
24 firrtl2verilog=""
25 xfirrtl="../xfirrtl"
26 abcprog="$toolsdir/../../yosys-abc"
27
28 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
29 ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
30 fi
31
32 while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
33 case "$opt" in
34 x)
35 use_xsim=true ;;
36 m)
37 use_modelsim=true ;;
38 G)
39 warn_iverilog_git=true ;;
40 l)
41 libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
42 w)
43 genvcd=true ;;
44 k)
45 keeprunning=true ;;
46 j)
47 makejmode=true ;;
48 v)
49 verbose=true ;;
50 r)
51 backend_opts="$backend_opts -norename" ;;
52 e)
53 backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
54 f)
55 frontend="$OPTARG" ;;
56 s)
57 [[ "$OPTARG" == /* ]] || OPTARG="$PWD/$OPTARG"
58 scriptfiles="$scriptfiles $OPTARG" ;;
59 p)
60 scriptopt="$OPTARG" ;;
61 n)
62 autotb_opts="$autotb_opts -n $OPTARG" ;;
63 S)
64 autotb_opts="$autotb_opts -seed $OPTARG" ;;
65 I)
66 include_opts="$include_opts -I $OPTARG"
67 xinclude_opts="$xinclude_opts -i $OPTARG"
68 minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
69 A)
70 abcprog="$OPTARG" ;;
71 -)
72 case "${OPTARG}" in
73 xfirrtl)
74 xfirrtl="${!OPTIND}"
75 OPTIND=$(( $OPTIND + 1 ))
76 ;;
77 firrtl2verilog)
78 firrtl2verilog="${!OPTIND}"
79 OPTIND=$(( $OPTIND + 1 ))
80 ;;
81 *)
82 if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
83 echo "Unknown option --${OPTARG}" >&2
84 fi
85 ;;
86 esac;;
87 *)
88 echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
89 exit 1
90 esac
91 done
92
93 compile_and_run() {
94 exe="$1"; output="$2"; shift 2
95 if [ "${2##*.}" == "sv" ]; then
96 language_gen="-g2012"
97 else
98 language_gen="-g2005"
99 fi
100
101 if $use_modelsim; then
102 altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
103 /opt/altera/$altver/modelsim_ase/bin/vlib work
104 /opt/altera/$altver/modelsim_ase/bin/vlog $minclude_opts +define+outfile=\"$output\" "$@"
105 /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench
106 elif $use_xsim; then
107 xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; )
108 /opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
109 /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
110 else
111 iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
112 vvp -n "$exe"
113 fi
114 }
115
116 shift $((OPTIND - 1))
117
118 for fn
119 do
120 bn=${fn%.*}
121 ext=${fn##*.}
122 if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
123 echo "Invalid argument: $fn" >&2
124 exit 1
125 fi
126 [[ "$bn" == *_tb ]] && continue
127
128 if $makejmode; then
129 status_prefix="Test: $bn "
130 else
131 status_prefix=""
132 echo -n "Test: $bn "
133 fi
134
135 if [ "$ext" == sv ]; then
136 frontend="$frontend -sv"
137 fi
138
139 rm -f ${bn}.{err,log,skip}
140 mkdir -p ${bn}.out
141 rm -rf ${bn}.out/*
142
143 body() {
144 cd ${bn}.out
145 fn=$(basename $fn)
146 bn=$(basename $bn)
147 refext=v
148
149 rm -f ${bn}_ref.fir
150 if [[ "$ext" == "v" ]]; then
151 egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
152 elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
153 $abcprog -c "read_aiger ../${fn}; write ${bn}_ref.${refext}"
154 else
155 refext=$ext
156 cp ../${fn} ${bn}_ref.${refext}
157 fi
158
159 if [ ! -f ../${bn}_tb.v ]; then
160 "$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
161 else
162 cp ../${bn}_tb.v ${bn}_tb.v
163 fi
164 if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
165 compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} $libs \
166 "$toolsdir"/../../techlibs/common/simlib.v \
167 "$toolsdir"/../../techlibs/common/simcells.v
168 if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
169
170 test_count=0
171 test_passes() {
172 "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
173 compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
174 ${bn}_tb.v ${bn}_syn${test_count}.v $libs \
175 "$toolsdir"/../../techlibs/common/simlib.v \
176 "$toolsdir"/../../techlibs/common/simcells.v
177 if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
178 $toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
179 test_count=$(( test_count + 1 ))
180 }
181
182 if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.${refext}; then
183 touch ../${bn}.skip
184 return
185 fi
186
187 if [ -n "$scriptfiles" ]; then
188 test_passes -f "$frontend $include_opts" ${bn}_ref.${refext} $scriptfiles
189 elif [ -n "$scriptopt" ]; then
190 test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${refext}
191 elif [ "$frontend" = "verific" ]; then
192 test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -all; opt; memory;;"
193 elif [ "$frontend" = "verific_gates" ]; then
194 test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -gates -all; opt; memory;;"
195 else
196 test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${refext}
197 test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
198 if [ -n "$firrtl2verilog" ]; then
199 if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
200 "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
201 $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
202 test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
203 fi
204 fi
205 fi
206 touch ../${bn}.log
207 }
208
209 if $verbose; then
210 echo ".."
211 echo "Output written to console." > ${bn}.err
212 ( set -ex; body; )
213 else
214 ( set -ex; body; ) > ${bn}.err 2>&1
215 fi
216
217 did_firrtl=""
218 if [ -f ${bn}.out/${bn}_ref.fir ]; then
219 did_firrtl="+FIRRTL "
220 fi
221 if [ -f ${bn}.log ]; then
222 mv ${bn}.err ${bn}.log
223 echo "${status_prefix}${did_firrtl}-> ok"
224 elif [ -f ${bn}.skip ]; then
225 mv ${bn}.err ${bn}.skip
226 echo "${status_prefix}-> skip"
227 else
228 echo "${status_prefix}${did_firrtl}-> ERROR!"
229 if $warn_iverilog_git; then
230 echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
231 fi
232 $keeprunning || exit 1
233 fi
234 done
235
236 exit 0