Merge remote-tracking branch 'origin/master' into xc7mux
[yosys.git] / tests / tools / autotest.sh
1 #!/usr/bin/env bash
2
3 libs=""
4 genvcd=false
5 use_xsim=false
6 use_modelsim=false
7 verbose=false
8 keeprunning=false
9 makejmode=false
10 frontend="verilog -noblackbox"
11 backend_opts="-noattr -noexpr -siminit"
12 autotb_opts=""
13 include_opts=""
14 xinclude_opts=""
15 minclude_opts=""
16 scriptfiles=""
17 scriptopt=""
18 toolsdir="$(cd $(dirname $0); pwd)"
19 warn_iverilog_git=false
20 # The following are used in verilog to firrtl regression tests.
21 # Typically these will be passed as environment variables:
22 #EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
23 # The tests are skipped if firrtl2verilog is the empty string (the default).
24 firrtl2verilog=""
25 xfirrtl="../xfirrtl"
26
27 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
28 ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
29 fi
30
31 while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
32 case "$opt" in
33 x)
34 use_xsim=true ;;
35 m)
36 use_modelsim=true ;;
37 G)
38 warn_iverilog_git=true ;;
39 l)
40 libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
41 w)
42 genvcd=true ;;
43 k)
44 keeprunning=true ;;
45 j)
46 makejmode=true ;;
47 v)
48 verbose=true ;;
49 r)
50 backend_opts="$backend_opts -norename" ;;
51 e)
52 backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
53 f)
54 frontend="$OPTARG" ;;
55 s)
56 [[ "$OPTARG" == /* ]] || OPTARG="$PWD/$OPTARG"
57 scriptfiles="$scriptfiles $OPTARG" ;;
58 p)
59 scriptopt="$OPTARG" ;;
60 n)
61 autotb_opts="$autotb_opts -n $OPTARG" ;;
62 S)
63 autotb_opts="$autotb_opts -seed $OPTARG" ;;
64 I)
65 include_opts="$include_opts -I $OPTARG"
66 xinclude_opts="$xinclude_opts -i $OPTARG"
67 minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
68 -)
69 case "${OPTARG}" in
70 xfirrtl)
71 xfirrtl="${!OPTIND}"
72 OPTIND=$(( $OPTIND + 1 ))
73 ;;
74 firrtl2verilog)
75 firrtl2verilog="${!OPTIND}"
76 OPTIND=$(( $OPTIND + 1 ))
77 ;;
78 *)
79 if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
80 echo "Unknown option --${OPTARG}" >&2
81 fi
82 ;;
83 esac;;
84 *)
85 echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
86 exit 1
87 esac
88 done
89
90 compile_and_run() {
91 exe="$1"; output="$2"; shift 2
92 if $use_modelsim; then
93 altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
94 /opt/altera/$altver/modelsim_ase/bin/vlib work
95 /opt/altera/$altver/modelsim_ase/bin/vlog $minclude_opts +define+outfile=\"$output\" "$@"
96 /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench
97 elif $use_xsim; then
98 xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; )
99 /opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
100 /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
101 else
102 iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
103 vvp -n "$exe"
104 fi
105 }
106
107 shift $((OPTIND - 1))
108
109 for fn
110 do
111 bn=${fn%.*}
112 ext=${fn##*.}
113 if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
114 echo "Invalid argument: $fn" >&2
115 exit 1
116 fi
117 [[ "$bn" == *_tb ]] && continue
118
119 if $makejmode; then
120 status_prefix="Test: $bn "
121 else
122 status_prefix=""
123 echo -n "Test: $bn "
124 fi
125
126 rm -f ${bn}.{err,log,skip}
127 mkdir -p ${bn}.out
128 rm -rf ${bn}.out/*
129
130 body() {
131 cd ${bn}.out
132 fn=$(basename $fn)
133 bn=$(basename $bn)
134
135 rm -f ${bn}_ref.fir
136 if [[ "$ext" == "v" ]]; then
137 egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
138 else
139 "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
140 frontend="verilog -noblackbox"
141 fi
142
143 if [ ! -f ../${bn}_tb.v ]; then
144 "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
145 else
146 cp ../${bn}_tb.v ${bn}_tb.v
147 fi
148 if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
149 compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
150 "$toolsdir"/../../techlibs/common/simlib.v \
151 "$toolsdir"/../../techlibs/common/simcells.v
152 if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
153
154 test_count=0
155 test_passes() {
156 "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
157 compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
158 ${bn}_tb.v ${bn}_syn${test_count}.v $libs \
159 "$toolsdir"/../../techlibs/common/simlib.v \
160 "$toolsdir"/../../techlibs/common/simcells.v
161 if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
162 $toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
163 test_count=$(( test_count + 1 ))
164 }
165
166 if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.v; then
167 touch ../${bn}.skip
168 return
169 fi
170
171 if [ -n "$scriptfiles" ]; then
172 test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles
173 elif [ -n "$scriptopt" ]; then
174 test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
175 elif [ "$frontend" = "verific" ]; then
176 test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
177 elif [ "$frontend" = "verific_gates" ]; then
178 test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
179 else
180 test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
181 test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
182 if [ -n "$firrtl2verilog" ]; then
183 if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
184 "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
185 $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
186 test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
187 fi
188 fi
189 fi
190 touch ../${bn}.log
191 }
192
193 if $verbose; then
194 echo ".."
195 echo "Output written to console." > ${bn}.err
196 ( set -ex; body; )
197 else
198 ( set -ex; body; ) > ${bn}.err 2>&1
199 fi
200
201 did_firrtl=""
202 if [ -f ${bn}.out/${bn}_ref.fir ]; then
203 did_firrtl="+FIRRTL "
204 fi
205 if [ -f ${bn}.log ]; then
206 mv ${bn}.err ${bn}.log
207 echo "${status_prefix}${did_firrtl}-> ok"
208 elif [ -f ${bn}.skip ]; then
209 mv ${bn}.err ${bn}.skip
210 echo "${status_prefix}-> skip"
211 else
212 echo "${status_prefix}${did_firrtl}-> ERROR!"
213 if $warn_iverilog_git; then
214 echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
215 fi
216 $keeprunning || exit 1
217 fi
218 done
219
220 exit 0