10 frontend
="verilog -noblackbox"
11 backend_opts
="-noattr -noexpr -siminit"
18 toolsdir
="$(cd $(dirname $0); pwd)"
19 warn_iverilog_git
=false
20 # The following are used in verilog to firrtl regression tests.
21 # Typically these will be passed as environment variables:
22 #EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
23 # The tests are skipped if firrtl2verilog is the empty string (the default).
27 if [ ! -f $toolsdir/cmp_tbdata
-o $toolsdir/cmp_tbdata.c
-nt $toolsdir/cmp_tbdata
]; then
28 ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata
$toolsdir/cmp_tbdata.c
; ) ||
exit 1
31 while getopts xmGl
:wkjvref
:s
:p
:n
:S
:I
:-: opt
; do
38 warn_iverilog_git
=true
;;
40 libs
="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
50 backend_opts
="$backend_opts -norename" ;;
52 backend_opts
="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
56 [[ "$OPTARG" == /* ]] || OPTARG
="$PWD/$OPTARG"
57 scriptfiles
="$scriptfiles $OPTARG" ;;
59 scriptopt
="$OPTARG" ;;
61 autotb_opts
="$autotb_opts -n $OPTARG" ;;
63 autotb_opts
="$autotb_opts -seed $OPTARG" ;;
65 include_opts
="$include_opts -I $OPTARG"
66 xinclude_opts
="$xinclude_opts -i $OPTARG"
67 minclude_opts
="$minclude_opts +incdir+$OPTARG" ;;
72 OPTIND
=$
(( $OPTIND + 1 ))
75 firrtl2verilog
="${!OPTIND}"
76 OPTIND
=$
(( $OPTIND + 1 ))
79 if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
80 echo "Unknown option --${OPTARG}" >&2
85 echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
91 exe
="$1"; output
="$2"; shift 2
92 if $use_modelsim; then
93 altver
=$
( ls -v /opt
/altera
/ |
grep '^[0-9]' |
tail -n1; )
94 /opt
/altera
/$altver/modelsim_ase
/bin
/vlib work
95 /opt
/altera
/$altver/modelsim_ase
/bin
/vlog
$minclude_opts +define
+outfile
=\"$output\" "$@"
96 /opt
/altera
/$altver/modelsim_ase
/bin
/vsim
-c -do 'run -all; exit;' testbench
98 xilver
=$
( ls -v /opt
/Xilinx
/Vivado
/ |
grep '^[0-9]' |
tail -n1; )
99 /opt
/Xilinx
/Vivado
/$xilver/bin
/xvlog
$xinclude_opts -d outfile
=\"$output\" "$@"
100 /opt
/Xilinx
/Vivado
/$xilver/bin
/xelab
-R work.testbench
102 iverilog
$include_opts -Doutfile=\"$output\" -s testbench
-o "$exe" "$@"
107 shift $
((OPTIND
- 1))
113 if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
114 echo "Invalid argument: $fn" >&2
117 [[ "$bn" == *_tb
]] && continue
120 status_prefix
="Test: $bn "
126 rm -f ${bn}.
{err
,log
,skip
}
136 if [[ "$ext" == "v" ]]; then
137 egrep -v '^\s*`timescale' ..
/$fn > ${bn}_ref.
${ext}
139 "$toolsdir"/..
/..
/yosys
-f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ..
/${fn}
140 frontend
="verilog -noblackbox"
143 if [ ! -f ..
/${bn}_tb.v
]; then
144 "$toolsdir"/..
/..
/yosys
-f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v
${bn}_ref.v
146 cp ..
/${bn}_tb.v
${bn}_tb.v
148 if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v
; fi
149 compile_and_run
${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v
$libs \
150 "$toolsdir"/..
/..
/techlibs
/common
/simlib.v
151 if $genvcd; then mv testbench.vcd
${bn}_ref.vcd
; fi
155 "$toolsdir"/..
/..
/yosys
-b "verilog $backend_opts" -o ${bn}_syn
${test_count}.v
"$@"
156 compile_and_run
${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
157 ${bn}_tb.v ${bn}_syn${test_count}.v
$libs \
158 "$toolsdir"/..
/..
/techlibs
/common
/simlib.v \
159 "$toolsdir"/..
/..
/techlibs
/common
/simcells.v
160 if $genvcd; then mv testbench.vcd
${bn}_syn
${test_count}.vcd
; fi
161 $toolsdir/cmp_tbdata
${bn}_out_ref ${bn}_out_syn${test_count}
162 test_count
=$
(( test_count
+ 1 ))
165 if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP
${bn}_ref.v
; then
170 if [ -n "$scriptfiles" ]; then
171 test_passes
-f "$frontend $include_opts" ${bn}_ref.v
$scriptfiles
172 elif [ -n "$scriptopt" ]; then
173 test_passes
-f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
174 elif [ "$frontend" = "verific" ]; then
175 test_passes
-p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
176 elif [ "$frontend" = "verific_gates" ]; then
177 test_passes
-p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
179 test_passes
-f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
180 test_passes
-f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
181 if [ -n "$firrtl2verilog" ]; then
182 if test -z "$xfirrtl" ||
! grep "$fn" "$xfirrtl" ; then
183 "$toolsdir"/..
/..
/yosys
-b "firrtl" -o ${bn}_ref.fir
-f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
184 $firrtl2verilog -i ${bn}_ref.fir
-o ${bn}_ref.fir.v
185 test_passes
-f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
194 echo "Output written to console." > ${bn}.err
197 ( set -ex; body
; ) > ${bn}.err
2>&1
201 if [ -f ${bn}.out
/${bn}_ref.fir
]; then
202 did_firrtl
="+FIRRTL "
204 if [ -f ${bn}.log
]; then
205 mv ${bn}.err
${bn}.log
206 echo "${status_prefix}${did_firrtl}-> ok"
207 elif [ -f ${bn}.skip
]; then
208 mv ${bn}.err
${bn}.skip
209 echo "${status_prefix}-> skip"
211 echo "${status_prefix}${did_firrtl}-> ERROR!"
212 if $warn_iverilog_git; then
213 echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
215 $keeprunning ||
exit 1