3 # Note: You might need to install the Verilog::VCD package using CPAN..
7 use Verilog
::VCD
qw(parse_vcd list_sigs);
16 if ($ARGV[0] eq '-f') {
17 $from_time = +$ARGV[1];
22 if ($ARGV[0] eq '-t') {
33 print STDERR
"VCD2TXT - Convert VCD to tab-separated text file\n";
35 print STDERR
"Usage: $0 [-f from_time] [-t to_time] input.vcd [<signal regex> ...]\n";
40 my $vcd = parse_vcd
($ARGV[0]);
42 for my $node (keys $vcd) {
43 for my $net (@
{$vcd->{$node}->{'nets'}}) {
44 my $dump_this = $#ARGV == 0;
45 for (my $i = 1; $i <= $#ARGV; $i++) {
46 my $regex = $ARGV[$i];
47 $dump_this = 1 if ($net->{"hier"} . "." . $net->{"name"}) =~ /$regex/;
49 next unless $dump_this;
50 my $cached_value = "";
51 for my $tv (@
{$vcd->{$node}->{'tv'}}) {
52 $cached_value = $tv->[1], next if $from_time >= 0 and +$tv->[0] < $from_time;
53 next if $to_time >= 0 and +$tv->[0] > $to_time;
54 printf "%s\t%s\t%s\t%s\n", $node, $from_time, $net->{"hier"} . "." . $net->{"name"}, $cached_value
55 if $cached_value ne "" and $from_time >= 0 and +$tv->[0] > $from_time;
56 printf "%s\t%s\t%s\t%s\n", $node, $tv->[0], $net->{"hier"} . "." . $net->{"name"}, $tv->[1];