tests/various/abc9.ys

   1 read_verilog abc9.v
   2 design -save read
   3 hierarchy -top abc9_test027
   4 proc
   5 design -save gold
   6
   7 abc9 -lut 4
   8 check
   9 design -stash gate
  10
  11 design -import gold -as gold
  12 design -import gate -as gate
  13
  14 miter -equiv -flatten -make_assert -make_outputs gold gate miter
  15 sat -verify -prove-asserts -show-ports miter
  16
  17 design -load read
  18 hierarchy -top abc9_test028
  19 proc
  20
  21 abc9 -lut 4
  22 select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
  23 select -assert-count 1 t:unknown
  24 select -assert-none t:$lut t:unknown %% t: %D