tests/various/abc9.ys

   1 read_verilog abc9.v
   2 proc
   3 design -save gold
   4
   5 abc9 -lut 4
   6 check
   7 design -stash gate
   8
   9 design -import gold -as gold
  10 design -import gate -as gate
  11
  12 miter -equiv -flatten -make_assert -make_outputs gold gate miter
  13 sat -verify -prove-asserts -show-ports miter
  14