8 always @(posedge clk) begin
16 always @(posedge clk, posedge r) begin
24 always @(posedge clk, negedge r) begin
31 assign q = {q2, q1, q0};
36 parameter integer WIDTH = 1
39 output reg [WIDTH-1:0] Q
41 wire sysclk = testbench.sysclk;
42 always @(posedge sysclk)
48 always #5 sysclk = (sysclk === 1'b0);
51 always @(posedge sysclk) clk = (clk === 1'b0);
56 uut uut (.clk(clk), .d(d), .r(r), .e(e), .q(q_uut));
59 syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn));
62 prp prp (.clk(clk), .d(d), .r(r), .e(e), .q(q_prp));
65 a2s a2s (.clk(clk), .d(d), .r(r), .e(e), .q(q_a2s));
68 ffl ffl (.clk(clk), .d(d), .r(r), .e(e), .q(q_ffl));
74 if (q_uut !== q_syn) msg = "SYN";
75 if (q_uut !== q_prp) msg = "PRP";
76 if (q_uut !== q_a2s) msg = "A2S";
77 if (q_uut !== q_ffl) msg = "FFL";
78 $display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg);
79 if (msg != "OK") $finish;
84 $dumpfile("async.vcd");
85 $dumpvars(0, testbench);