tests/various/async.v

   1 `define MAXQ 2
   2 module uut (
   3         input clk,
   4         input d, r, e,
   5         output [`MAXQ:0] q
   6 );
   7         reg q0;
   8         always @(posedge clk) begin
   9                 if (r)
  10                         q0 <= 0;
  11                 else if (e)
  12                         q0 <= d;
  13         end
  14
  15         reg q1;
  16         always @(posedge clk, posedge r) begin
  17                 if (r)
  18                         q1 <= 0;
  19                 else if (e)
  20                         q1 <= d;
  21         end
  22
  23         reg q2;
  24         always @(posedge clk, negedge r) begin
  25                 if (!r)
  26                         q2 <= 0;
  27                 else if (!e)
  28                         q2 <= d;
  29         end
  30
  31         assign q = {q2, q1, q0};
  32 endmodule
  33
  34 `ifdef TESTBENCH
  35 module \$ff #(
  36         parameter integer WIDTH = 1
  37 ) (
  38         input [WIDTH-1:0] D,
  39         output reg [WIDTH-1:0] Q
  40 );
  41         wire sysclk = testbench.sysclk;
  42         always @(posedge sysclk)
  43                 Q <= D;
  44 endmodule
  45
  46 module testbench;
  47         reg sysclk;
  48         always #5 sysclk = (sysclk === 1'b0);
  49
  50         reg clk;
  51         always @(posedge sysclk) clk = (clk === 1'b0);
  52
  53         reg d, r, e;
  54
  55         wire [`MAXQ:0] q_uut;
  56         uut uut (.clk(clk), .d(d), .r(r), .e(e), .q(q_uut));
  57
  58         wire [`MAXQ:0] q_syn;
  59         syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn));
  60
  61         wire [`MAXQ:0] q_prp;
  62         prp prp (.clk(clk), .d(d), .r(r), .e(e), .q(q_prp));
  63
  64         wire [`MAXQ:0] q_a2s;
  65         a2s a2s (.clk(clk), .d(d), .r(r), .e(e), .q(q_a2s));
  66
  67         wire [`MAXQ:0] q_ffl;
  68         ffl ffl (.clk(clk), .d(d), .r(r), .e(e), .q(q_ffl));
  69
  70         task printq;
  71                 reg [5*8-1:0] msg;
  72                 begin
  73                         msg = "OK";
  74                         if (q_uut !== q_syn) msg = "SYN";
  75                         if (q_uut !== q_prp) msg = "PRP";
  76                         if (q_uut !== q_a2s) msg = "A2S";
  77                         if (q_uut !== q_ffl) msg = "FFL";
  78                         $display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg);
  79                         if (msg != "OK") $finish;
  80                 end
  81         endtask
  82
  83         initial if(0) begin
  84                 $dumpfile("async.vcd");
  85                 $dumpvars(0, testbench);
  86         end
  87
  88         initial begin
  89                 @(posedge clk);
  90                 d <= 0;
  91                 r <= 0;
  92                 e <= 0;
  93                 @(posedge clk);
  94                 e <= 1;
  95                 @(posedge clk);
  96                 e <= 0;
  97                 repeat (10000) begin
  98                         @(posedge clk);
  99                         printq;
 100                         d <= $random;
 101                         r <= $random;
 102                         e <= $random;
 103                 end
 104                 $display("PASS");
 105                 $finish;
 106         end
 107 endmodule
 108 `endif