tests/various/attrib05_port_conn.v

   1 module bar(clk, rst, inp, out);
   2   input  wire clk;
   3   input  wire rst;
   4   input  wire inp;
   5   output reg  out;
   6
   7   always @(posedge clk)
   8     if (rst) out <= 1'd0;
   9     else     out <= ~inp;
  10
  11 endmodule
  12
  13 module foo(clk, rst, inp, out);
  14   input  wire clk;
  15   input  wire rst;
  16   input  wire inp;
  17   output wire out;
  18
  19   bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
  20 endmodule
  21