tests/various/bug1480.ys

   1 read_verilog << EOF
   2 module top(...);
   3
   4 input signed [17:0] A;
   5 input signed [17:0] B;
   6 output X;
   7 output Y;
   8
   9 wire [35:0] P;
  10 assign P = A * B;
  11
  12 assign X = P[0];
  13 assign Y = P[35];
  14
  15 endmodule
  16 EOF
  17
  18 synth_xilinx