tests/various/bug1710.ys

   1 logger -werror "out of bounds"
   2 read_verilog <<EOT
   3 module Example;
   4
   5     parameter FLAG = 1;
   6     wire [3:0] inp;
   7
   8     reg out1;
   9     initial out1 = FLAG ? &inp[2:0] : &inp[4:0];
  10
  11     reg out2;
  12     initial
  13         if (FLAG)
  14             out2 = &inp[2:0];
  15         else
  16             out2 = &inp[4:0];
  17
  18     wire out3;
  19     assign out3 = FLAG ? &inp[2:0] : &inp[4:0];
  20
  21     wire out4;
  22     generate
  23         if (FLAG)
  24             assign out4 = &inp[2:0];
  25         else
  26             assign out4 = &inp[4:0];
  27     endgenerate
  28
  29 endmodule
  30 EOT