3 module top(input clk, input rst);
7 always @(posedge clk, posedge rst) begin
12 2'b00: state <= 2'b01;
13 2'b01: state <= 2'b10;
14 2'b10: state <= 2'b00;
18 sub sub_i(.i(state == 0));
32 # Make sure there is a driver
33 select -assert-any t:sub %ci %a w:* %i %ci c:* %i