tests/various/bug1781.ys

   1 read_verilog <<EOT
   2
   3 module top(input clk, input rst);
   4
   5 reg [1:0] state;
   6
   7 always @(posedge clk, posedge rst) begin
   8         if (rst)
   9                 state <= 0;
  10         else
  11                 case (state)
  12                         2'b00: state <= 2'b01;
  13                         2'b01: state <= 2'b10;
  14                         2'b10: state <= 2'b00;
  15                 endcase
  16 end
  17
  18 sub sub_i(.i(state == 0));
  19
  20 endmodule
  21
  22
  23 (* blackbox, keep *)
  24 module sub(input i);
  25 endmodule
  26
  27 EOT
  28
  29 proc
  30 fsm
  31
  32 # Make sure there is a driver
  33 select -assert-any t:sub %ci %a w:* %i %ci c:* %i